io.h

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#include <stdint.h>
#include <stddef.h>
#ifndef _IO_H
#define _IO_H
#define __IO volatile

#ifdef ARM_CM0
// Vyzobano z STM stm32f0xx.h
struct RCC_Type {
  __IO uint32_t CR;         
  __IO uint32_t CFGR;       
  __IO uint32_t CIR;        
  __IO uint32_t APB2RSTR;   
  __IO uint32_t APB1RSTR;   
  __IO uint32_t AHBENR;     
  __IO uint32_t APB2ENR;    
  __IO uint32_t APB1ENR;    
  __IO uint32_t BDCR;       
  __IO uint32_t CSR;        
  __IO uint32_t AHBRSTR;    
  __IO uint32_t CFGR2;      
  __IO uint32_t CFGR3;      
  __IO uint32_t CR2;        
} ;
struct GPIO_Type {
  __IO uint32_t MODER;        
  __IO uint16_t OTYPER;       
  uint16_t RESERVED0;         
  __IO uint32_t OSPEEDR;      
  __IO uint32_t PUPDR;        
  __IO uint16_t IDR;          
  uint16_t RESERVED1;         
  __IO uint16_t ODR;          
  uint16_t RESERVED2;         
  union {                     // Kompatibilita s F4 zavede trochu chaos, ale funkční - původně jeden 32.bit registr
    __IO uint32_t BSRR;         
    struct {                  // Jde takto rozdělit (jako v F4) na dva 16. bitové registry
      __IO uint16_t BSRRL;      
      __IO uint16_t BSRRH;      
    };
  };
  __IO uint32_t LCKR;         
  __IO uint32_t AFR[2];       
  __IO uint16_t BRR;          
  uint16_t RESERVED3;         
} ;

#define     PERIPH_BASE       ((uint32_t)    0x40000000)     
#define  AHBPERIPH_BASE       (PERIPH_BASE + 0x00020000)     
#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)     
#define        RCC_BASE       (AHBPERIPH_BASE  + 0x00001000) 
#define      GPIOC_BASE       (AHB2PERIPH_BASE + 0x00000800) 
#define  RCC_AHBENR_GPIOCEN   ((uint32_t)0x00080000)         
// board specific
#define LEDPORT_BASE  GPIOC_BASE                             
#define LEDCLK_GPIOEN RCC_AHBENR_GPIOCEN                     
#define LEDPIN        8                                      
#define DELAY_TIME    0x40000                                
#define DELAY_SYST    4000000                               
typedef enum {
  /******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
  NonMaskableInt_IRQn         = -14,    
  HardFault_IRQn              = -13,    
  SVC_IRQn                    = -5,     
  PendSV_IRQn                 = -2,     
  SysTick_IRQn                = -1,     
  /******  STM32F051x4/STM32F051x6/STM32F051x8 specific Interrupt Numbers **************************************/
  WWDG_IRQn                   = 0,      
  PVD_IRQn                    = 1,      
  RTC_IRQn                    = 2,      
  FLASH_IRQn                  = 3,      
  RCC_IRQn                    = 4,      
  EXTI0_1_IRQn                = 5,      
  EXTI2_3_IRQn                = 6,      
  EXTI4_15_IRQn               = 7,      
  TSC_IRQn                    = 8,      
  DMA1_Channel1_IRQn          = 9,      
  DMA1_Channel2_3_IRQn        = 10,     
  DMA1_Channel4_5_IRQn        = 11,     
  ADC1_COMP_IRQn              = 12,     
  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     
  TIM1_CC_IRQn                = 14,     
  TIM2_IRQn                   = 15,     
  TIM3_IRQn                   = 16,     
  TIM6_DAC_IRQn               = 17,     
  TIM14_IRQn                  = 19,     
  TIM15_IRQn                  = 20,     
  TIM16_IRQn                  = 21,     
  TIM17_IRQn                  = 22,     
  I2C1_IRQn                   = 23,     
  I2C2_IRQn                   = 24,     
  SPI1_IRQn                   = 25,     
  SPI2_IRQn                   = 26,     
  USART1_IRQn                 = 27,     
  USART2_IRQn                 = 28,     
  CEC_CAN_IRQn                = 30      
} IRQn_Type;

#define __CM0_REV                 0 
#define __MPU_PRESENT             0 
#define __NVIC_PRIO_BITS          2 
#define __Vendor_SysTickConfig    0 
#include "core_cm0.h"

#endif // ARM_CM0
#ifdef ARM_CM4

// Vyzobano z STM stm32f4xx.h
// RCC
struct RCC_Type {
  __IO uint32_t CR;            
  __IO uint32_t PLLCFGR;       
  __IO uint32_t CFGR;          
  __IO uint32_t CIR;           
  __IO uint32_t AHB1RSTR;      
  __IO uint32_t AHB2RSTR;      
  __IO uint32_t AHB3RSTR;      
  uint32_t      RESERVED0;     
  __IO uint32_t APB1RSTR;      
  __IO uint32_t APB2RSTR;      
  uint32_t      RESERVED1[2];  
  __IO uint32_t AHBENR;        
  __IO uint32_t AHB2ENR;       
  __IO uint32_t AHB3ENR;       
  uint32_t      RESERVED2;     
  __IO uint32_t APB1ENR;       
  __IO uint32_t APB2ENR;       
  uint32_t      RESERVED3[2];  
  __IO uint32_t AHB1LPENR;     
  __IO uint32_t AHB2LPENR;     
  __IO uint32_t AHB3LPENR;     
  uint32_t      RESERVED4;     
  __IO uint32_t APB1LPENR;     
  __IO uint32_t APB2LPENR;     
  uint32_t      RESERVED5[2];  
  __IO uint32_t BDCR;          
  __IO uint32_t CSR;           
  uint32_t      RESERVED6[2];  
  __IO uint32_t SSCGR;         
  __IO uint32_t PLLI2SCFGR;    
} ;
// GPIO
struct GPIO_Type {
  __IO uint32_t MODER;    
  __IO uint32_t OTYPER;   
  __IO uint32_t OSPEEDR;  
  __IO uint32_t PUPDR;    
  __IO uint32_t IDR;      
  __IO uint32_t ODR;      
  __IO uint16_t BSRRL;    
  __IO uint16_t BSRRH;    
  __IO uint32_t LCKR;     
  __IO uint32_t AFR[2];   
} ;

#define PERIPH_BASE           ((uint32_t)0x40000000)
#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
// board specific
#define LEDPORT_BASE  GPIOD_BASE
#define LEDPIN        15
#define LEDCLK_GPIOEN ((uint32_t)0x00000008)
#define DELAY_TIME    0x200000
#define DELAY_SYST    8000000                       
typedef enum IRQn {
  /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  NonMaskableInt_IRQn         = -14,    
  MemoryManagement_IRQn       = -12,    
  BusFault_IRQn               = -11,    
  UsageFault_IRQn             = -10,    
  SVCall_IRQn                 = -5,     
  DebugMonitor_IRQn           = -4,     
  PendSV_IRQn                 = -2,     
  SysTick_IRQn                = -1,     
  /******  STM32 specific Interrupt Numbers **********************************************************************/
  WWDG_IRQn                   = 0,      
  PVD_IRQn                    = 1,      
  TAMP_STAMP_IRQn             = 2,      
  RTC_WKUP_IRQn               = 3,      
  FLASH_IRQn                  = 4,      
  RCC_IRQn                    = 5,      
  EXTI0_IRQn                  = 6,      
  EXTI1_IRQn                  = 7,      
  EXTI2_IRQn                  = 8,      
  EXTI3_IRQn                  = 9,      
  EXTI4_IRQn                  = 10,     
  DMA1_Stream0_IRQn           = 11,     
  DMA1_Stream1_IRQn           = 12,     
  DMA1_Stream2_IRQn           = 13,     
  DMA1_Stream3_IRQn           = 14,     
  DMA1_Stream4_IRQn           = 15,     
  DMA1_Stream5_IRQn           = 16,     
  DMA1_Stream6_IRQn           = 17,     
  ADC_IRQn                    = 18,     
  CAN1_TX_IRQn                = 19,     
  CAN1_RX0_IRQn               = 20,     
  CAN1_RX1_IRQn               = 21,     
  CAN1_SCE_IRQn               = 22,     
  EXTI9_5_IRQn                = 23,     
  TIM1_BRK_TIM9_IRQn          = 24,     
  TIM1_UP_TIM10_IRQn          = 25,     
  TIM1_TRG_COM_TIM11_IRQn     = 26,     
  TIM1_CC_IRQn                = 27,     
  TIM2_IRQn                   = 28,     
  TIM3_IRQn                   = 29,     
  TIM4_IRQn                   = 30,     
  I2C1_EV_IRQn                = 31,     
  I2C1_ER_IRQn                = 32,     
  I2C2_EV_IRQn                = 33,     
  I2C2_ER_IRQn                = 34,     
  SPI1_IRQn                   = 35,     
  SPI2_IRQn                   = 36,     
  USART1_IRQn                 = 37,     
  USART2_IRQn                 = 38,     
  USART3_IRQn                 = 39,     
  EXTI15_10_IRQn              = 40,     
  RTC_Alarm_IRQn              = 41,     
  OTG_FS_WKUP_IRQn            = 42,     
  TIM8_BRK_TIM12_IRQn         = 43,     
  TIM8_UP_TIM13_IRQn          = 44,     
  TIM8_TRG_COM_TIM14_IRQn     = 45,     
  TIM8_CC_IRQn                = 46,     
  DMA1_Stream7_IRQn           = 47,     
  FSMC_IRQn                   = 48,     
  SDIO_IRQn                   = 49,     
  TIM5_IRQn                   = 50,     
  SPI3_IRQn                   = 51,     
  UART4_IRQn                  = 52,     
  UART5_IRQn                  = 53,     
  TIM6_DAC_IRQn               = 54,     
  TIM7_IRQn                   = 55,     
  DMA2_Stream0_IRQn           = 56,     
  DMA2_Stream1_IRQn           = 57,     
  DMA2_Stream2_IRQn           = 58,     
  DMA2_Stream3_IRQn           = 59,     
  DMA2_Stream4_IRQn           = 60,     
  ETH_IRQn                    = 61,     
  ETH_WKUP_IRQn               = 62,     
  CAN2_TX_IRQn                = 63,     
  CAN2_RX0_IRQn               = 64,     
  CAN2_RX1_IRQn               = 65,     
  CAN2_SCE_IRQn               = 66,     
  OTG_FS_IRQn                 = 67,     
  DMA2_Stream5_IRQn           = 68,     
  DMA2_Stream6_IRQn           = 69,     
  DMA2_Stream7_IRQn           = 70,     
  USART6_IRQn                 = 71,     
  I2C3_EV_IRQn                = 72,     
  I2C3_ER_IRQn                = 73,     
  OTG_HS_EP1_OUT_IRQn         = 74,     
  OTG_HS_EP1_IN_IRQn          = 75,     
  OTG_HS_WKUP_IRQn            = 76,     
  OTG_HS_IRQn                 = 77,     
  DCMI_IRQn                   = 78,     
  CRYP_IRQn                   = 79,     
  HASH_RNG_IRQn               = 80,      
  FPU_IRQn                    = 81      
} IRQn_Type;

#define __CM4_REV                 0x0001  
#define __MPU_PRESENT             1       
#define __NVIC_PRIO_BITS          4       
#define __Vendor_SysTickConfig    0       
#include "core_cm4.h"

#endif // ARM_CM4
typedef struct RCC_Type  RCC_TypeDef;
typedef struct GPIO_Type GPIO_TypeDef;
// Funkce obsluhující vektor reset je bez návratu, nemusí tedy nic uklízet na zásobník.
// Proto ji můžeme definovat jako naked, pro případné zkrácení kódu. Není to však nutné (alespoň pro gcc).
#define NAKED __attribute__((naked))

// Naplň část ram definovaným obsahem - debug stacku.
static inline void fillram (void) {
  __ASM volatile (
    "ldr  r0, =0x20000800\n\t"  // od
    "ldr  r1, =0x20001800\n\t"  // do
    "ldr  r2, =0xDEADBEEF\n"    // obsah
    "floop:\n\t"
    "str  r2, [r0, #0]\n\t"
    "add  r0, r0,  #4\n\t"
    "cmp  r0, r1\n\t"
    "bne  floop\n\t"
//  "bkpt 0\n"
    );
}


#endif// _IO_H