ARM_minimal.
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#include <io.h>
Veřejné atributy | |
__IO uint32_t | CR |
__IO uint32_t | CFGR |
__IO uint32_t | CIR |
__IO uint32_t | APB2RSTR |
__IO uint32_t | APB1RSTR |
__IO uint32_t | AHBENR |
__IO uint32_t | APB2ENR |
__IO uint32_t | APB1ENR |
__IO uint32_t | BDCR |
__IO uint32_t | CSR |
__IO uint32_t | AHBRSTR |
__IO uint32_t | CFGR2 |
__IO uint32_t | CFGR3 |
__IO uint32_t | CR2 |
Reset and clock control
__IO uint32_t RCC_Type::AHBENR |
RCC AHB peripheral clock register, Address offset: 0x14
__IO uint32_t RCC_Type::AHBRSTR |
RCC AHB peripheral reset register, Address offset: 0x28
__IO uint32_t RCC_Type::APB1ENR |
RCC APB1 peripheral clock enable register, Address offset: 0x1C
__IO uint32_t RCC_Type::APB1RSTR |
RCC APB1 peripheral reset register, Address offset: 0x10
__IO uint32_t RCC_Type::APB2ENR |
RCC APB2 peripheral clock enable register, Address offset: 0x18
__IO uint32_t RCC_Type::APB2RSTR |
RCC APB2 peripheral reset register, Address offset: 0x0C
__IO uint32_t RCC_Type::BDCR |
RCC Backup domain control register, Address offset: 0x20
__IO uint32_t RCC_Type::CFGR |
RCC clock configuration register, Address offset: 0x04
__IO uint32_t RCC_Type::CFGR2 |
RCC clock configuration register 2, Address offset: 0x2C
__IO uint32_t RCC_Type::CFGR3 |
RCC clock configuration register 3, Address offset: 0x30
__IO uint32_t RCC_Type::CIR |
RCC clock interrupt register, Address offset: 0x08
__IO uint32_t RCC_Type::CR |
RCC clock control register, Address offset: 0x00
__IO uint32_t RCC_Type::CR2 |
RCC clock control register 2, Address offset: 0x34
__IO uint32_t RCC_Type::CSR |
RCC clock control & status register, Address offset: 0x24